Patent Number: 6,165,695

Title: Thin resist with amorphous silicon hard mask for via etch application

Abstract: A method of forming a via structure is provided. In the method, a dielectric layer is formed on an anti-reflective coating (ARC) layer covering a first metal layer; and an amorphous silicon layer is formed on the dielectric layer. An ultra-thin photoresist layer is formed on the amorphous silicon layer, and the ultra-thin photoresist layer is patterned with short wavelength radiation to define a pattern for a via. The patterned ultra-thin photoresist layer is used as a mask during a first etch step to transfer the via pattern to the amorphous silicon layer. The first etch step includes an etch chemistry that is selective to the amorphous silicon layer over the ultra-thin photoresist layer and the dielectric layer. The amorphous silicon layer is employed as a hard mask during a second etch step to form a contact hole corresponding to the via pattern by etching portions of the dielectric layer.

Inventors: Yang; Chih Yuh (San Jose, CA), Lyons; Christopher F. (Fremont, CA), Levinson; Harry J. (Saratoga, CA), Nguyen; Khanh B. (San Mateo, CA), Wang; Fei (San Jose, CA), Bell; Scott A. (San Jose, CA)

Assignee: Advanced Micro Devices, Inc.

International Classification: H01L 21/02 (20060101); H01L 21/70 (20060101); H01L 21/033 (20060101); H01L 21/027 (20060101); H01L 21/768 (20060101); H01L 21/311 (20060101); G03C 005/00 ()

Expiration Date: 12/26/2017