Patent Number: 6,165,889

Title: Process for forming trenches and contacts during the formation of a semiconductor memory device

Abstract: A method of forming a contact to a semiconductor memory device feature comprises the steps of forming a first oxide layer over a feature such as a semiconductor substrate or a conductive line or plate, then forming a hard mask over the first oxide layer. A first patterned resist layer is formed on the hard mask, then the hard mask is patterned using the first resist layer as a pattern. The first resist layer is removed and a second oxide layer is formed over the hard mask. A second patterned resist layer is formed over the second oxide layer and the second oxide layer is etched using the second resist layer as a pattern while, during a single etch step, the first oxide layer is etched using the hard mask as a pattern, the hard mask functioning as an etch stop. The second resist layer is removed and a conductive layer is formed over the second dielectric layer and the hard mask, with the conductive layer (including any adhesion layers required to adhere the conductive layer to the underlying layer) contacting the feature and forming contacts. The conductive layer is then planarized.

Inventors: Ireland; Philip J. (Boise, ID)

Assignee: Micron Technology, Inc.

International Classification: H01L 21/70 (20060101); H01L 21/768 (20060101); H01L 021/4763 ()

Expiration Date: 12/26/2017