Patent Number: 6,166,395

Title: Amorphous silicon interconnect with multiple silicon layers

Abstract: In one aspect, the invention includes a semiconductor processing method comprising depositing a silicon layer over a substrate at different deposition temperatures which at least include increasing the deposition temperature through a range of from about 550.degree. C. to about 560.degree. C. In another aspect, the invention includes a semiconductor processing method comprising, in an uninterrupted deposition process, depositing a silicon layer which comprises an essentially amorphous silicon region, an essentially polycrystalline silicon region, and a transition region interconnecting the essentially amorphous silicon region and the essentially polycrystalline silicon region, the essentially amorphous silicon region having an amorphous silicon content which is greater than or equal to about 90 weight percent of a total material of the amorphous silicon region, the essentially polycrystalline silicon region having a polycrystalline silicon content which is greater than or equal to about 90 weight percent of a total material of the polycrystalline silicon region, the transition comprising an amorphous silicon content and a polycrystalline silicon content, the transition region being defined as a region having both a lower amorphous silicon content than the essentially amorphous silicon region and a lower polycrystalline silicon content than the essentially polycrystalline silicon region, the transition region being at least 45 Angstroms thick.

Inventors: Smith; Keith (Boise, ID), Wald; Phillip G. (Boise, ID)

Assignee: Micron Technology, Inc.

International Classification: H01L 21/205 (20060101); H01L 21/285 (20060101); H01L 21/768 (20060101); H01L 21/70 (20060101); H01L 21/02 (20060101); H01L 029/04 (); H01L 031/036 (); H01L 031/0376 (); H01L 031/20 (); H01L 023/48 ()

Expiration Date: 12/26/2013