Patent Number: 6,166,408

Title: Hexagonally symmetric integrated circuit cell

Abstract: An apparatus and method for fabrication a hexagonally symmetric cell, (e.g., a dynamic random access memory cell (100)). The cell can comprise a bitline contact (38), storage node contacts (32) hexagonally surrounding the bitline contact (38), storage nodes (36) also surrounding the bitline contact (38), a wordline (30) portions of which form field effect transistor gates. Large distances between bitline contacts (38) and storage node contacts (32) cause large problems during photolithography because dark areas are difficult to achieve when using Levenson Phaseshift. Because Levenson Phaseshift depends on wave cancellations between nearby features, commonly known as destructive interferences, the resultant printability of the pattern is largely a function of the symmetry and separation distances. When non-symmetries in the pattern occur, the result is weaker cancellations of fields (i.e. between features) and a large loss of image contrast and depth of focus during the printing step. The net result are defects, which increase device failure, can be significantly reduced by the geometry modifications disclosed herein.

Inventors: Nishimura; Akitoshi (Tsuchiura, JP), Okuno; Yasutoshi (Tsukuba, JP), Khamankar; Rajesh (Irving, TX), Palmer; Shane R. (Dallas, TX)

Assignee: Texas Instruments Incorporated

International Classification: H01L 21/70 (20060101); H01L 21/8242 (20060101); H01L 27/108 (20060101); H01L 027/108 ()

Expiration Date: 12/26/2017