Patent Number: 6,166,409

Title: Flash EPROM memory cell having increased capacitive coupling

Abstract: A flash EPROM cell (10) is disclosed having increased capacitive coupling between a floating gate (28) and a control gate (32). Vertical structural elements (34a and 34b) are formed on field oxide regions (20) on opposing sides of the flash EPROM cell channel 20, in the channel width direction. The structural elements (34a and 34b) include relatively vertical faces. The floating gate (28) conformally cover the channel 20 and the vertical faces of the structural elements (34a and 34b). The control gate (32) conformally covers the floating gate (28). The vertical displacement introduced by the structural elements (34a and 34b) increases the overlap area between the floating gate (28) and the control gate (32) without increasing the overlap area of the floating gate (28) and the channel 20, resulting in increased capacitive coupling between the control gate (32) and the floating gate (28). A process is disclosed which enables the formation of the above structural elements (34a and 34b) with dimensions that are smaller than those normally achievable by the minimum resolution of lithography equipment.

Inventors: Ratnam; Perumal (Fremont, CA), Shrivastava; Ritu (Fremont, CA)

Assignee: Alliance Semiconductor Corporation

International Classification: H01L 21/02 (20060101); H01L 21/28 (20060101); H01L 29/66 (20060101); H01L 29/423 (20060101); H01L 29/40 (20060101); H01L 29/788 (20060101); H01L 029/788 ()

Expiration Date: 12/26/2017