Patent Number: 6,166,410

Title: MONOS flash memory for multi-level logic and method thereof

Abstract: The present invention provides a structure and method of manufacturing split gate MONOS multi-level logic memory device. The memory device has a poly stacked gate transistor 20A in series with a MONOS transistor 24A. The device has a novel operation to achieve multi-level memory storage (e.g., 4 voltage states). The method begins by forming a tunnel oxide layer 30 on the surface of a semiconductor substrate 10. The substrate having a stacked gate channel area 20 and a MONOS channel area 24 in the active regions. A poly floating gate electrode 32 is formed over the stacked gate channel region 20. A ONO layer having a memory nitride layer is formed over the floating gate 32 and the tunnel oxide layer over the MONOS channel region 24. A control gate electrode 44 is formed over the ONO layer 41 spanning across the poly floating gate electrode 32 and the MONOS channel region 24. Source/drain regions 50 51 are formed in the substrate. A poly flash transistor 20A and a MONOS flash transistor 24A combine to form the 4 level logic memory cell of the invention.

Inventors: Lin; Ruei-Ling (Kaohsiung, TW), Hsu; Ching-Hsiang (Hsin-chu, TW), Liang; Mong-Song (Hsin-chu, TW)

Assignee: Taiwan Semiconductor Manufacturing Company

International Classification: H01L 21/70 (20060101); H01L 21/02 (20060101); H01L 21/28 (20060101); G11C 11/56 (20060101); H01L 27/115 (20060101); H01L 29/66 (20060101); H01L 21/8246 (20060101); H01L 21/8247 (20060101); H01L 29/788 (20060101); H01L 027/148 ()

Expiration Date: 12/26/2017