Patent Number: 6,166,419

Title: Semiconductor memory device

Abstract: The present invention aims to prevent the thickness of the element separation insulating film of the high voltage withstanding area from being thinned and reliability of the memory cell from being reduced. Element separation insulating films are formed on a surface of a silicon substrate. A silicon oxide film, serving as a gate insulating film of a high voltage withstanding area, is formed on the surface of the silicon substrate. A first polycrystalline silicon film is deposited on the oxide film and the element separation insulating films, and a first resist pattern is formed on the polycrystalline silicon film of the high voltage withstanding area and the low voltage withstanding area. The resist pattern is used as a mask to etch the polycrystalline silicon film. After separating the resist pattern, the silicon oxide film of the cell area is removed, and an oxide-nitride film, serving as a gate insulating film of the cell area is formed on the surface of the silicon substrate of the cell area. Therefore, it is possible to prevent the thickness of the element separation insulating film of high voltage withstanding area from being thinned and prevent reliability of the memory cell from being reduced.

Inventors: Araki; Yoshiko (Kanagawa-ken, JP)

Assignee: Kabushiki Kaisha Toshiba

International Classification: H01L 27/115 (20060101); H01L 27/105 (20060101); H01L 21/70 (20060101); H01L 21/8247 (20060101); H01L 029/00 ()

Expiration Date: 12/26/2013