Patent Number: 6,166,420

Title: Method and structure of high and low K buried oxide for SoI technology

Abstract: A method and structure for forming an integrated circuit wafer comprises forming a substrate having first and second portions, depositing a first insulator over the substrate, patterning the first insulator such that the first insulator remains only over the first portion, depositing a second insulator over substrate (the first insulator has different thermal dissipation characteristics than the second insulator), polishing the second insulator to form a planar surface, and attaching a silicon film over the first insulator and the second insulator.

Inventors: Gauthier, Jr.; Robert J. (Hinesburg, VT), Schepis; Dominic J. (Wappingers Falls, NY), Voldman; Steven H. (South Burlington, VT)

Assignee: International Business Machines Corporation

International Classification: H01L 21/70 (20060101); H01L 21/762 (20060101); H01L 029/00 (); H01L 023/58 ()

Expiration Date: 12/26/2013