Patent Number: 6,166,423

Title: Integrated circuit having a via and a capacitor

Abstract: An integrated circuit including a capacitor and a method of manufacturing the capacitor simultaneously while forming a dual damascene via. A first interconnect layer is formed upon a first interlevel dielectric. Openings corresponding to vias and capacitors extend through a second interlevel dielectric to the first interconnect layer. A conductor is deposited in the via openings. An insulator is deposited in the openings and on the conductor in the via openings. A trench is then etched into the upper portion of the via openings while simultaneously removing the insulator from the conductor in the via openings. A conductor is then deposited in the openings and in the trenches and chemical-mechanical polishing (CMP) is used to pattern the conductor. A third interlevel dielectric is then deposited, openings are formed extending to the conductors, and third interconnect layer conductors are deposited and patterned.

Inventors: Gambino; Jeffrey P. (Gaylordsville, CT), Jaso; Mark A. (Manassas, VA), Kotecki; David E. (Hopewell Junction, NY)

Assignee: International Business Machines Corporation

International Classification: H01L 21/70 (20060101); H01L 21/02 (20060101); H01L 21/768 (20060101); H01L 21/8242 (20060101); H01L 27/08 (20060101); H01L 029/00 ()

Expiration Date: 12/26/2017