Patent Number: 6,166,427

Title: Integration of low-K SiOF as inter-layer dielectric for AL-gapfill application

Abstract: A method for producing a dielectric layer in a semiconductor product includes two steps. The first step is forming a fluorinated layer (e.g. SiOF or fluorosilicate glass ("FSG")) which includes a material formed in part with fluorine. The second step is forming a fill layer (e.g. SiO.sub.2) above the fluorinated layer. The fill layer is substantially free of materials formed in part with fluorine. A top surface of the fill layer can be planarized. Surface treatments and oxide caps can be applied to the planarized surface to form fluorine barriers if part of the fluorinated layer is exposed to higher layers. Such a method, and a semiconductor device or integrated circuit manufactured according to the method, allow the dielectric constant of an inter-layer dielectric ("ILD") to be lowered while also minimizing the complexity and expense of the manufacturing process.

Inventors: Huang; Richard J. (Cupertino, CA), Iacoponi; John A. (San Jose, CA)

Assignee: Advanced Micro Devices, Inc.

International Classification: C23C 16/40 (20060101); H01L 21/70 (20060101); H01L 21/02 (20060101); H01L 21/768 (20060101); H01L 21/316 (20060101); H01L 23/52 (20060101); H01L 23/532 (20060101); H01L 023/58 (); H01L 021/31 (); H01L 021/469 ()

Expiration Date: 12/26/2017