Patent Number: 6,166,558

Title: Method for measuring gate length and drain/source gate overlap

Abstract: The invention provides a method and apparatus for calculating gate length and source/drain gate overlap, by measuring gate capacitance. The invention uses previously known fringe capacitance C.sub.fr and unit capacitance C.sub.OX. The invention measures gate capacitance C.sub.g, when the gate is accumulatively biased, and solves for overlap capacitance C.sub.OV using the equation C.sub.OV =(C.sub.g -2C.sub.fr)/2 or C.sub.OV =(C.sub.gg -C.sub.gb -2C.sub.fr)/2. The invention then measures the gate capacitance C.sub.g when the gate to source/drain voltage is set to inversion bias and a zero voltage is applied between the source/drain and the substrate, and solves for the channel capacitance C.sub.ch using the equation C.sub.ch =C.sub.g -2C.sub.fr -2C.sub.OV. The invention calculates the channel capacitance C.sub.ch where C.sub.ch =C.sub.g -2C.sub.fr -2C.sub.OV and then calculates gate length where gate length L.sub.g =(2C.sub.OV +C.sub.ch)/C.sub.OX and the effective gate length L.sub.eff =C.sub.ch /C.sub.OX. The invention further calculates source/drain gate overlap L.sub.OV, by setting L.sub.OV =C.sub.OV /C.sub.OX.

Inventors: Jiang; Chun (San Jose, CA), Long; Wei (Sunnyvale, CA), Ling; Zicheng G. (Sunnyvale, CA), Liu; Yowjuang W. (San Jose, CA)

Assignee: Advanced Micro Devices, Inc.

International Classification: H01L 21/66 (20060101); H01L 029/78 ()

Expiration Date: 12/26/2017