Patent Number: 6,166,563

Title: Method and apparatus for dual mode output buffer impedance compensation

Abstract: A method and circuit for programming an output buffer having a first output driver for producing a first signaling level with a first programmable strength and a second output driver for producing a second signaling level with a second programmable strength. The method includes coupling a test resistor between a source of the second signaling level and a mode terminal, sensing a first level at the mode terminal, and uncoupling the test resistor from the mode terminal. If the first level is between the second signaling level and a reference level, then programming the output buffer with reference to an unterminated transmission line coupled to the mode terminal. Otherwise, programming the output buffer with reference to an external resistor coupled between a source of the first signaling level and the mode terminal. The circuit includes a first counter coupled to the first comparator to produce a first value responsive to the mode flag, the mode terminal, and the reference level. A first latch, coupled to the first counter, provides the adjusted first value to the first output driver. A second latch, coupled to the second counter, provides the adjusted second value to the second output driver.

Inventors: Volk; Andrew M. (Granite Bay, CA), Asperheim; Jennefer (El Dorado Hills, CA), Lin; Hou-Sheng (Sacramento, CA), Trivedi; Romesh (Folsom, CA)

Assignee: Intel Corporation

International Classification: H03K 19/00 (20060101); H03K 19/0185 (20060101); H03K 019/0175 ()

Expiration Date: 12/26/2017