Patent Number: 6,166,564

Title: Control circuit for clock enable staging

Abstract: A control circuit for clock enable staging between first and second clock macros wherein each clock macro produces a clock signal at an output in response to a transition of a global clock signal when an enable signal has been activated. The control circuit comprises a latch element having a first input coupled to the output of the first clock macro, a second input of the latch element is coupled to the output of the second clock macro, and an output node coupled to the enable input of the second clock macro. The output node of the latch element activates the enable input of the second clock macro responsive to the clock signal at the output of the first clock macro, and inactivates the enable input of the second clock macro responsive to the clock signal at the output of the second clock macro.

Inventors: Rosen; Eitan E. (Haifa, IL)

Assignee: Intel Corporation

International Classification: H03K 19/096 (20060101); H03K 019/00 ()

Expiration Date: 12/26/2017