Patent Number: 6,166,572

Title: Voltage-controlled delay line, direct phase controlled voltage-controlled oscillator, clock/data recovery circuit, and clock/data recovery apparatus

Abstract: A clock/data recovery device employs a phase-locked loop that supplies a single clock signal and a control voltage signal to at least one clock/data recovery circuit. The clock/data recovery circuit has a voltage-controlled delay line or direct phase controlled voltage-controlled oscillator that generates a multiple-phase clock signal, which is used to recover a clock signal and data from a received data signal. The voltage-controlled delay line or direct phase controlled vottage-controlled oscillator has a cascade or ring of voltage controlled logic gates, with propagation delays controlled by the control voltage signal from the phase-locked loop, and additional logic gates that supply the clock signal from the phase-locked loop to a selectable one of the voltage-controlled logic gates.

Inventors: Yamaoka; Nobusuke (Tokyo, JP)

Assignee: Oki Electric Industry Co., Ltd.

International Classification: H03L 7/099 (20060101); H03L 7/081 (20060101); H03L 7/07 (20060101); H03L 7/08 (20060101); H03K 5/13 (20060101); H03K 5/00 (20060101); H04L 7/033 (20060101); H03L 007/07 ()

Expiration Date: 12/26/2013