Patent Number: 6,166,578

Title: Circuit arrangement to compensate non-linearities in a resistor, and method

Abstract: A circuit arrangement (100) is coupled to a resistor (150) having at least two portions (110, 120). The arrangement (100) provides a substantially linear performance of the resistor (150). The arrangement (100) comprises a differential difference amplifier (160) (with input stages (170, 180) and output stage (190)) and a feedback unit (130). The input stages (170, 180) modify first (161) and second (162) measurement signals (e.g., (V.sub.B -V.sub.A) and (V.sub.A -GND), respectively) from the resistor portions (110, 120) to intermediate signals (OPH, OMH, OPL, OML). The output stage (190) differentially amplifies sums (at nodes 191, 192) of the intermediate signals and provides a control signal (CONTROL) which corresponds to a magnitude difference between the first and second measurement signals. The feedback unit (130) receives the control signal and supplies a corrective current (I) to the resistor (150) to offset non-linearity.

Inventors: Shor; Joseph (Raanana, IL), Koifman; Vladimir (Rishon le Zion, IL), Afek; Yachin (Kfar Saba, IL)

Assignee: Motorola Inc.

International Classification: G01K 7/21 (20060101); G01K 7/16 (20060101); H03L 005/00 ()

Expiration Date: 12/26/2017