Patent Number: 6,166,579

Title: Digitally controlled signal magnitude control circuit

Abstract: A digitally controlled signal attenuator circuit which allows an incoming DC-clamped signal to be selectively attenuated using a set of digital control signals while maintaining its DC clamping. Multiple stages of such a circuit can be cascaded to provide for multiple forms of signal attenuation without affecting the clamping. Preferred forms of the attenuator circuit use pass transistors and transmission gates as switches for selectively altering the resistance values of resistive circuits connected in shunt to and in series with the signal being attenuated. In the case of where the subject signal is a variable DC signal such a brightness control voltage, such circuit configurations also allow the output signal voltage range to include values which are more negative than the DC clamp voltage as well as more positive.

Inventors: Hojabri; Peyman (San Jose, CA), Morrish; Andrew (Saratoga, CA)

Assignee: National Semiconductor Corporation

International Classification: H03G 3/30 (20060101); H03L 005/00 ()

Expiration Date: 12/26/2017