Patent Number: 6,166,590

Title: Current mirror and/or divider circuits with dynamic current control which are useful in applications for providing series of reference currents, subtraction, summation and comparison

Abstract: Circuit useful as current mirror and/or current divider has a circuit topology containing mirror and reference transistor pairs, respectively provided by MOS P and N type transistors for the up and down mirrors. The mirror transistor in each pair is followed by a buffer transistor which provides the current output. The topology obtains equal input and output currents through the DC biasing of the reference and mirror transistors by providing equality of the D to S and G to S voltages operative in both the reference and mirror transistors of both mirrors. The topology provides matched performance for the up and down current mirrors with very high mirroring accuracy, design insensitive up and down mirrored current, excellent operation over a wide power supply range, temperature insensitive precision, and the possibility of conveniently obtaining a wide range of current divisions. This topology is appropriate for those applications in which precise current handling and division is necessary such as high accuracy A/D and D/A converters, reference cells, current subtractors, and high precision current comparators.

Inventors: Friedman; Eby (Rochester, NY), Secareanu; Radu M. (Rochester, NY)

Assignee: The University of Rochester

International Classification: G05F 3/08 (20060101); G05F 3/26 (20060101); G05F 001/10 ()

Expiration Date: 12/26/2013