Patent Number: 6,166,606

Title: Phase and frequency locked clock generator

Abstract: A phase locked loop is described for generating an output clock signal that is both synchronizing with a synchronizing signal and oscillating at substantially the same frequency as required by the system. The phase locked loop as disclosed compares the time durations of the output clock of a voltage-controlled oscillator with the system clock for N cycles. A correction signal is then generated by comparing these two time durations, and the correction signal is fed back to the voltage-controlled oscillator to eliminate the difference in the time durations. In addition, the voltage-controlled oscillator is also synchronized with the synchronizing signal by using the synchronizing signal as a reset.

Inventors: Tsyrganovich; Anatoliy V. (San Jose, CA)

Assignee: Zilog, Inc.

International Classification: G09G 3/20 (20060101); H03L 7/085 (20060101); H03L 7/08 (20060101); H03L 7/07 (20060101); H04N 5/12 (20060101); H04N 5/445 (20060101); H04N 5/06 (20060101); H03L 007/06 ()

Expiration Date: 12/26/2017