Patent Number: 6,166,743

Title: Method and system for improved z-test during image rendering

Abstract: Aspects for effectively improving the throughput in a rasterization pipeline for image rendering in a computer system are provided. A method aspect includes receiving data for a chosen number of pixels in a Z-test mechanism of the rasterization pipeline, performing Z-test determinations for the chosen number of pixels in a same clock cycle to achieve faster processing in the Z-test mechanism than other portions of the rasterization pipeline, and tagging the chosen number of pixels based upon the Z-test determinations to indicate pass/fail status for rendering. A circuit aspect includes at least one memory device for storing pixel data, a Z-test mechanism, the Z-test mechanism within the rasterization pipeline and coupled to the at least one memory device for determining a pass/fail rendering status for a plurality of pixels received in parallel from the at least one memory means, and a plurality of mechanisms forming a portion of the rasterization pipeline following the Z-test mechanism, the plurality of mechanisms for processing pixel data with a pass status sequentially.

Inventors: Tanaka; Greg L. (Sunnyvale, CA)

Assignee: Silicon Magic Corporation

International Classification: G06T 15/10 (20060101); G06T 15/40 (20060101); G06T 015/40 ()

Expiration Date: 12/26/2017