Patent Number: 6,166,786

Title: Semiconductor element with N channel and P region connected only to the channel and liquid crystal display device using the same

Abstract: To prevent an n-channel thin-film transistor from being deteriorated by hot holes generated in a gate-negative pulse mode, a thin polysilicon film 10 is provided with a p-type semiconductor region 13 in contact with a channel region 14. The p-type semiconductor region 13 is electrically connected to nowhere except the channel region 14. Holes induced on the surface due to a gate-negative pulse are further supplied from the p-type semiconductor region 13. An electric field established by the gate-negative pulse is relaxed by the holes, fewer hot holes are injected into the gate oxide film, and the TFT characteristics are less deteriorated.

Inventors: Ohkubo; Tatsuya (Hitachinaka, JP), Kawachi; Genshiro (Hitachi, JP), Mikami; Yoshiro (Hitachi, JP), Masuda; Kazuhito (Hitachi, JP), Kageyama; Hiroshi (Hitachi, JP)

Assignee: Hitachi, Ltd.

International Classification: G02F 1/13 (20060101); G02F 1/1368 (20060101); H01L 21/02 (20060101); H01L 29/66 (20060101); H01L 27/12 (20060101); H01L 21/336 (20060101); H01L 29/786 (20060101); G02F 001/136 (); H01L 029/04 ()

Expiration Date: 12/26/2017