Patent Number: 6,166,939

Title: Method and apparatus for selective match line pre-charging in a content addressable memory

Abstract: Match line control circuits are used to selectively charge corresponding match lines in response to the valid bits. If the valid bit is asserted, thereby indicating the valid data is stored in the CAM row, the match line control circuit pre-charges the match line to enable the match line to be responsive to compare operation between a comparand word and data stored in the row. If the valid bit is de-asserted, thereby indicating that any data stored in the row is invalid, the match line control circuit disables the match line by forcing a mismatch condition between the comparand word and data stored in the row. In one embodiment, the match line control circuit includes a pull-up transistor coupled between the match line and a supply voltage and having a gate responsive to the valid bit. In other embodiments, the match line control circuit further includes a pull-down transistor coupled between the match line and a supply voltage and having a gate responsive to a complement of the valid bit.

Inventors: Nataraj; Bindiganavale S. (Cupertino, CA), Srinivasan; Varadarajan (Los Altos Hills, CA), Khanna; Sandeep (Santa Clara, CA)

Assignee: Net Logic Microsystems

International Classification: G11C 15/00 (20060101); G11C 15/04 (20060101); G11C 015/00 ()

Expiration Date: 12/26/2013