Patent Number: 6,166,940

Title: Semiconductor memory device having a plurality of storage regions

Abstract: In a semiconductor memory device, a semiconductor chip has a plurality of storage regions, a circuit region, and a wiring region having a plurality of first signal lines and a plurality of second signal lines. Each second signal line is laid out between the first signal lines adjacent to each other and has a wiring length smaller than that of each first signal line. The wiring region has a portion where wiring lines are densely laid out and a portion where wiring lines are sparsely laid out. The second signal lines are laid out in the wiring region of the semiconductor chip while being separated from the first signal lines adjacent to the second signal lines by a minimum distance between signal lines or more, which is determined on the basis of a design rule. The plurality of first signal lines are laid out in the wiring region of the semiconductor chip at an interval (K) obtained by K.gtoreq.2S+L (where S is a value representing the minimum distance, and L is a value representing a wiring width of the second signal lines).

Inventors: Ozeki; Seiji (Tokyo, JP)

Assignee: NEC Corporation

International Classification: G11C 5/06 (20060101); G11C 005/02 ()

Expiration Date: 12/26/2017