Patent Number: 6,166,941

Title: Relaxed layout for storage nodes for dynamic random access memories

Abstract: A memory cell structure (10) includes a plurality of bit lines (12) and intersecting word lines (14). Bit line contacts (16) are spaced evenly apart on an associated bit line (12). A plurality of storage nodes (20) and associated storage node contacts (18) are provided. Storage nodes (20) and storage node contacts (2) are spaced evenly apart along the associated bit line (12). The storage nodes (20) and storage node contacts (18) are offset with respect to storage nodes (20) and storage node contacts (18) placed along adjacent bit lines (12).

Inventors: Yoshida; Hiroyuki (Plano, TX), Nagata; Toshiyuki (Plano, TX)

Assignee: Texas Instruments Incorporated

International Classification: H01L 27/108 (20060101); G11C 005/02 ()

Expiration Date: 12/26/2017