Patent Number: 6,166,942

Title: Embedded DRAM architecture with local data drivers and programmable number of data read and data write lines

Abstract: A DRAM architecture configures memory cells into a predetermined number of arrays. Each array has its own row decoders and sense amplifiers. A data path circuit containing local drivers and data read and write lines is associated with each of the arrays in a first direction. The respective connections between the array and data path circuit utilize IO lines that are considerably shorter than the IO lines used in prior art architectures. Using this unique arrangement of data path circuits and memory arrays as a building block, a DRAM architecture of increased capacity can be constructed by simply placing additional data paths and memory arrays on to the semiconductor device in a second direction orthogonal to the first direction.

Inventors: Vo; Huy T. (Boise, ID), Merritt; Todd A. (Boise, ID), Bunker; Layne G. (Boise, ID)

Assignee: Micron Technology, Inc.

International Classification: G11C 7/18 (20060101); G11C 11/409 (20060101); G11C 7/10 (20060101); G11C 7/00 (20060101); G11C 11/4097 (20060101); G11C 005/06 ()

Expiration Date: 12/26/2017