Patent Number: 6,166,950

Title: Nonvolatile semiconductor storage device

Abstract: In a nonvolatile semiconductor memory device in which a plurality of threshold values are set to store multi-level data in a memory cell, bits of multi-bit data are separately written into a memory cell according to an address signal or a control signal to effect the reading and erasing. Concretely, the memory array is so constituted that it can be accessed by three-dimensional address of X, Y and Z, and multi-bit data in the memory cell is discriminated by the Z-address.

Inventors: Yamada; Naoki (Sakado, JP), Sato; Hiroshi (Ome, JP), Tsujikawa; Tetsuya (Hamura, JP), Miyazawa; Kazuyuki (Hidaka, JP)

Assignee: Hitachi, Ltd.

International Classification: G11C 11/56 (20060101); G11C 011/34 ()

Expiration Date: 12/26/2017