Patent Number: 6,166,953

Title: Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein

Abstract: A semiconductor device having and electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

Inventors: Matsubara; Kiyoshi (Higashimurayama, JP), Yashiki; Naoki (Kodaira, JP), Baba; Shiro (Kokubunji, JP), Ito; Takashi (Kokubunji, JP), Mukai; Hirofumi (Musashino, JP), Sato; Masanao (Tokyo, JP), Terasawa; Masaaki (Akishima, JP), Kuroda; Kenichi (Tachikawa, JP), Shiba; Kazuyoshi (Kodaira, JP)

Assignee: Hitachi, Ltd.

International Classification: G06F 15/76 (20060101); G06F 15/78 (20060101); G11C 16/10 (20060101); G11C 16/16 (20060101); G11C 16/06 (20060101); G11C 16/26 (20060101); G11C 16/30 (20060101); H01L 21/70 (20060101); G11C 16/04 (20060101); H01L 27/115 (20060101); H01L 21/8247 (20060101); H01L 27/105 (20060101); G11C 016/04 ()

Expiration Date: 12/26/2017