Patent Number: 6,166,958

Title: Semiconductor memory device, method for manufacturing the same, and method for controlling the same

Abstract: There is disclosed a memory cell which has a diffusion layers constituting source/drain areas formed on a p-type silicon substrate surface, and a channel area formed between the diffusion layers. Above the channel area, an insulating film of a laminated structure is formed of a silicon oxide film, a silicon nitride film and a silicon oxide film. A gate electrode is formed on the upper surface of the insulating film of the laminated structure. The gate electrode is used as a word line. Moreover, an interlayer insulating film is formed between the diffusion layer and the gate electrode. By injecting hot electrons from the substrate to the silicon nitride film in the insulating film of the laminated structure, data is written. The silicon nitride film and the diffusion layer are partially overlapped in a vertical direction, and an offset portion is disposed between the silicon nitride film and the diffusion layer.

Inventors: Naruke; Kiyomi (Sagamihara, JP), Maekawa; Shinichi (Kanagawa-ken, JP)

Assignee: Kabushiki Kaisha Toshiba

International Classification: H01L 27/115 (20060101); G11C 16/04 (20060101); H01L 21/70 (20060101); H01L 21/8247 (20060101); G11C 016/04 ()

Expiration Date: 12/26/2013