Patent Number: 6,166,963

Title: Dual port memory with synchronized read and write pointers

Abstract: A FIFO stack is implemented using a DPRAM. One of the ports of the DPRAM is used to add elements to the FIFO stack, and the other port is used to remove elements from the FIFO stack. The ports operate in separate clock domains. A synchronization circuit coordinates the read and write operations across the clock domains.

Inventors: Wen; Sheung-Fan (Sunnyvale, CA)

Assignee: National Semiconductor Corporation

International Classification: G06F 5/06 (20060101); G06F 5/10 (20060101); G11C 7/10 (20060101); G11C 007/00 ()

Expiration Date: 12/26/2017