Patent Number: 6,166,964

Title: Semiconductor memory and method of controlling data therefrom

Abstract: A semiconductor memory, such as a multibit DRAM, has a multiple cell array banks, each having multiple cell arrays. Rows of sense amplifiers are located near each of the cell arrays and extend in a first direction. Multiple rows of transfer switches, also extending in the first direction, are located adjacent to each of the cell array banks. A first data bus, which extends in a second direction which is perpendicular to the first direction, connects the sense amplifiers with the transfer switches. Multiple data buffer rows extend in the first direction near the transfer switches. A second data bus, extending in the first direction, connects the transfer switches with the data buffers. A layout pitch is defined by a spacing between adjacent lines of the first data bus. The transfer switches are placed in accordance with the defined layout pitch and the data buffers are placed according to a layout pitch determined by multiplying the defined layout pitch by the number of cell array banks.

Inventors: Aikawa; Tadao (Kawasaki, JP)

Assignee: Fujitsu Limited

International Classification: G11C 11/4096 (20060101); G11C 11/409 (20060101); G11C 7/10 (20060101); G11C 11/4097 (20060101); G11C 007/00 ()

Expiration Date: 12/26/2017