Patent Number: 6,166,970

Title: Priority determining apparatus using the least significant bit and CAS latency signal in DDR SDRAM device

Abstract: Disclosed is a DDR SDRAM device capable of inputting and outputting a plurality of data within one period of a clock; and, more particularly, a priority determining apparatus for determining data output priority between even and odd data. The DDR SDRAM device according to the present invention includes a priority signal generator for receiving a least significant bit of a column address signal and a first control signal which is activated when read or write operation is carried out and for generating a priority signal to determine an order of output of the even and odd data stored in each of the pipeline latch circuits.

Inventors: Yun; Mi-Kyung (Ichon, KR)

Assignee: Hyundai Electronics Industries Co., Ltd.

International Classification: G11C 7/10 (20060101); G11C 007/00 ()

Expiration Date: 12/26/2017