Patent Number: 6,166,972

Title: Semiconductor memory device and defect repair method for semiconductor memory device

Abstract: In a semiconductor memory device, rows of normal cell array blocks are selected by 13-bit row addresses corresponding to a refresh period of 8 kc respectively, so that the selected rows are successively refreshed. A spare memory array block is selected by a 12-bit row address for 4 kc excluding the most significant row address in the 13-bit row addresses corresponding to the row addresses of 8 kc. Thus, the semiconductor memory device can effectively carry out defect repair without reducing the yield also when a spare memory cell is inferior in data retention ability.

Inventors: Hidaka; Hideto (Tokyo, JP)

Assignee: Mitsubishi Denki Kabushiki Kaisha

International Classification: G11C 11/406 (20060101); G11C 29/24 (20060101); G11C 29/00 (20060101); G11C 29/04 (20060101); G11C 29/50 (20060101); G11C 007/00 ()

Expiration Date: 12/26/2017