Patent Number: 6,166,973

Title: Memory device with multiple-bit data pre-fetch function

Abstract: The present invention is a memory device having a multiple-bit data pre-fetch function wherein the operation of a redundancy checking circuit for comparing addresses and redundant addresses and checking the coincidence or non-coincidence thereof is started with timing prior to performing the last data fetches. The address signals are supplied with the same timing as the supply of the write commands, wherefore it is not always necessary for the operation of comparing the address signals against the redundant addresses of the memory cells, where the switch to the redundant cell array was performed, to have to wait until all of the multiple-bit data to be fetched. Accordingly, with the present invention, the redundancy checking operation is started before all of the data are fetched. In the case of a 2-bit data pre-fetch, the redundancy checking operation is started after the first datum has been fetched, and before the second bit of data is fetched. That being so, it is possible to begin the decoder operation with timing that is faster by precisely the period of the redundancy checking operation, wherefore it becomes possible to perform write operations to the memory cells with faster timing.

Inventors: Shinozaki; Naoharu (Kawasaki, JP)

Assignee: Fujitsu, Limited

International Classification: G11C 7/10 (20060101); G11C 29/00 (20060101); G11C 007/00 ()

Expiration Date: 12/26/2017