Patent Number: 6,166,976

Title: Multiple equilibration circuits for a single bit line

Abstract: According to one embodiment, a memory device comprises a bit line operable to access a memory cell. The bit line has a first end and a second end. A first equilibration circuit is coupled to the first end of the bit line, and a second equilibration circuit is coupled to the second end of the bit line. The first and second equilibration circuits cooperate to pre-charge the bit line. According to another embodiment, an embedded-process memory device comprises a p-well and a deep n-well formed into a substrate. A retrograde well is formed into the deep n-well. An equilibration circuit for pre-charging a bit line is formed into the retrograde well.

Inventors: Ong; Adrian E. (Pleasanton, CA)

Assignee: G-Link Technology

International Classification: G11C 7/12 (20060101); G11C 7/00 (20060101); H01L 27/108 (20060101); G11C 007/00 ()

Expiration Date: 12/26/2017