Patent Number: 6,166,987

Title: Nonvolatile semiconductor memory device having row decoder

Abstract: A nonvolatile semiconductor memory device is provided in which a negative voltage is applied to a gate electrode of a memory cell transistor during an erase mode. The memory device includes a row decoder circuit having an N-channel transistor connected to a word line. The N-channel transistor is provided on a P-type well region of a semiconductor substrate. A negative voltage is applied to the P-type well region during the erase mode, while ground potential is applied thereto during another modes.

Inventors: Atsumi; Shigeru (Tokyo, JP), Tanaka; Sumio (Tokyo, JP)

Assignee: Kabushiki Kaisha Toshiba

International Classification: G11C 8/00 (20060101); G11C 008/00 ()

Expiration Date: 12/26/2013