Patent Number: 6,166,988

Title: Semiconductor memory device using one common address bus line between address buffers and column predecoder

Abstract: A semiconductor memory device, includes: an external address buffer for buffering a first address signal to generate a buffered address signal; a delay for delaying the buffered address signal for a predetermined time to generate a delayed address signal; an internal address buffer for buffering the buffered address signal and the delayed address signal to generate a second address signal; a common address bus line; a switching unit responsive to a control signal for selectively coupling one of the buffered address signal, the delayed address signal and the second address signal as a selected address signal to said common address bus line; and a column predecoder for predecoding the selected address signal transferred via said common address bus line.

Inventors: Ryu; Je-Hun (Ichon-shi, KR), Han; Jong-Hee (Ichon-shi, KR)

Assignee: Hyundai Electronics Industries Co., Ltd.

International Classification: G11C 8/00 (20060101); G11C 8/06 (20060101); G11C 008/00 ()

Expiration Date: 12/26/2017