Patent Number: 6,166,990

Title: Clock reproduction circuit that can reproduce internal clock signal correctly in synchronization with external clock signal

Abstract: A frequency determination circuit generating a clock signal phase-locking with an external clock signal at a coarse precision and a fine adjust circuit generating an internal synchronizing signal phase-locking with the external clock signal at a fine precision are provided. The fine adjust circuit has a function of adjusting the phase of the frequency determination circuit when phase synchronization is to be carried out exceeding the adjust range thereof. The frequency determination circuit and the fine adjust circuit receive a clock power supply voltage. A clock reproduction circuit is provided which generates an internal clock signal phase-locking with an external clock signal or a reference clock signal stably even when the operating environment changes.

Inventors: Ooishi; Tsukasa (Hyogo, JP), Hanzawa; Satoru (Tokyo, JP), Nakatsuka; Kiyoshi (Ibaraki, JP)

Assignee: Mitsubishi Denki Kabushiki Kaisha

International Classification: G11C 7/22 (20060101); G11C 7/00 (20060101); G11C 8/18 (20060101); G11C 8/00 (20060101); G11C 11/407 (20060101); G11C 11/4076 (20060101); G11C 008/00 ()

Expiration Date: 12/26/2017