Patent Number: 6,166,991

Title: Circuit, architecture and method for reducing power consumption in a synchronous integrated circuit

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate (i) an internal select signal and (ii) a control signal in response to one or more chip select signals. The second circuit may be configured to generate a sleep signal in response to (i) said control signal and (ii) a clock signal.

Inventors: Phelan; Cathal (Mountain View, CA)

Assignee: Cypress Semiconductor Corp.

International Classification: G11C 5/14 (20060101); G11C 008/00 ()

Expiration Date: 12/26/2017