Patent Number: 6,166,993

Title: Synchronous semiconductor memory device

Abstract: A control signal generator, which decodes external control signals and generates internal control signals, is divided into a synchronous circuit and a timing adjustment circuit. The synchronous circuit includes latch circuits that respond to internal clock signals complementary to each other. It generates, in synchronization with the internal clock signals, state transition signals indicating operating modes. The timing adjustment circuit adjusts timings of the internal control signals with respect to rising or falling edges of these state transition signals. Thus, the design of the control signal generator is simple.

Inventors: Yamauchi; Tadaaki (Hyogo, JP)

Assignee: Mitsubishi Denki Kabushiki Kaisha

International Classification: G11C 7/22 (20060101); G11C 7/00 (20060101); G11C 7/10 (20060101); G11C 8/18 (20060101); G11C 8/00 (20060101); G11C 008/00 ()

Expiration Date: 12/26/2013