Patent Number: 6,167,001

Title: Method and apparatus for measuring setup and hold times for element microelectronic device

Abstract: A microelectronic device such as a Field-Programmable Gate Array (FPGA) includes a large number of elements which can be individually configured or programmed to provide a desired logical functionality. Input and output pins enable external connection of the elements. Each element is configurable to produce an output in response to a first pulse which is applied more than a minimum length of time after a second pulse. The first pulse can be a clock pulse, and the second pulse can be a data pulse, in which case the minimum length of time is the setup time for the element. Each element of a device is tested by repeatedly applying first and second pulses to the device with a delay of the second pulse relative to the first pulse being progressively changed from a first value until a second value corresponding to the minimum length of time is reached as indicated by a transition between the output being produced and the output not being produced. The element is then scanned using the first and second pulses and reference pulses with the delay set at the second value to determine the minimum length of time. The scanning procedure can also be used to measure a hold time, a time difference between input and output pulses, or a time difference between two output pulses.

Inventors: Wu; Yiding (Los Gatos, CA)

Assignee: Xilinx, Inc.

International Classification: G01R 29/02 (20060101); G01R 29/027 (20060101); G04F 10/00 (20060101); G04F 008/00 (); G04F 010/00 (); G01R 031/28 (); G06F 017/50 ()

Expiration Date: 12/26/2017