Patent Number: 6,167,026

Title: Programmable error control circuit

Abstract: In a loop network system, a method and apparatus for automatic bypass of a node port associated with a hub port when the node port generates a number of errors beyond a threshold level. In one aspect, a programmable error control circuit provides this automatic bypass. The tolerance level is set through programmable parameters including a number of errors as well as a time interval to evaluate the number of errors detected. After a node port has been bypassed by the error control circuit, the error control circuit continues to monitor the error generation of the node port. When that error generation has reached an acceptable tolerance level, the error control circuit automatically reinserts the node port into the loop. The error control circuit provides statistical reporting on the number of errors as well as the number of bypasses generated at a particular hub port.

Inventors: Brewer; David (Anaheim, CA), Hashemi; Hossein (Mission Viejo, CA), Henson; Karl M. (Rancho Santa Margarita, CA)

Assignee: Emulex Corporation

International Classification: H04L 1/00 (20060101); H04L 12/437 (20060101); H04L 12/427 (20060101); H04L 12/433 (20060101); H04L 12/44 (20060101); H04J 003/14 ()

Expiration Date: 12/26/2017