Patent Number: 6,167,101

Title: Apparatus and method for correcting a phase of a synchronizing signal

Abstract: The present invention discloses an apparatus and a method for correcting the phase of a synchronizing signal. A best clock timing on latching the data input can be achieved by the apparatus and the method provided. The apparatus of the present invention includes: a phase adjusting circuit for adjusting the phase; a phase lock loop being responsive to the phase adjusting circuit for generating a clock pulse signal; a latching circuit for generating a latched data pattern of the data input; a comparing circuit for comparing the latched pattern with the data input; and a switching circuit for varying a time delay of the phase adjusting circuit. The method of the present invention includes the following steps. At first, the phase of the synchronizing signal is delayed and a clock pulse signal is generated from a phase delayed synchronizing signal. Next, a test pattern is latched as a latched pattern by referencing the clock pulse signal. The latched pattern is then compared with the test pattern. If the latched pattern is different from the test pattern, a phase delay of the synchronizing signal is adjusted. The above steps of delaying the phase, generating the clock pulse signal, latching the test pattern, comparing the latched pattern, and adjusting the phase delay are repeated until the latched pattern is coincident with the test pattern.

Inventors: Yang; Her-Shin (Tainan Hsien, TW), Chen; Chein-Pin (Tainan Hsien, TW), Wang; Chih-Wei (Hsinchu, TW)

Assignee: Industrial Technology Research Institute

International Classification: G09G 5/18 (20060101); H03L 7/087 (20060101); H03L 7/081 (20060101); H03L 7/08 (20060101); H04N 5/12 (20060101); H03D 003/24 ()

Expiration Date: 12/26/2017