Patent Number: 6,167,109

Title: Compact buffer design for serial I/O

Abstract: A buffer design for use in digital signal processing for providing parallel shifting of digital data and serial output of the shifted data. The buffer includes an input shift register for receiving and shifting an input digital word, and one or more parallel shift registers connected to the input shift register for receiving and parallel shifting the shifted digital word output by the input shift register. An output shift register is connected to the parallel shift registers for shifting and serially outputting the shifted data word. The use of parallel shift registers in the inventive buffer allows for a more efficient use of chip surface area in the buffer design, thereby increasing overall chip yield and reducing chip cost.

Inventors: Mecklai; Hussein K. (Whitehall, PA), Webb; Andrew Lawrence (Hamilton, NJ)

Assignee: Lucent Technologies Inc.

International Classification: G06F 5/01 (20060101); G11C 19/00 (20060101); G11C 019/00 ()

Expiration Date: 12/26/2017