Patent Number: 6,167,134

Title: External resistor and method to minimize power dissipation in DC holding circuitry for a communication system

Abstract: A CMOS implementation for a DC holding circuit in direct access arrangement (DAA) circuitry is disclosed that provides desirable inductive behavior while minimizing power dissipation required by the CMOS integrated circuit, particularly at high loop currents. The DC holding circuitry disclosed may include MOS transistors located on a CMOS integrated circuit and an off-chip power dissipating resistor that acts to dissipate power external to the CMOS integrated circuit. The CMOS implementation disclosed also allows a path for drawing DC current to power other CMOS circuits (e.g., ADCs and DACs) in the CMOS integrated circuit.

Inventors: Scott; Jeffrey W. (Austin, TX), Sooch; Navdeep S. (Austin, TX), Welland; David R. (Austin, TX)

Assignee: Silicon Laboratories, Inc.

International Classification: H03M 1/42 (20060101); H04M 1/57 (20060101); H03M 1/38 (20060101); H04M 19/00 (20060101); H04M 11/06 (20060101); H04L 25/06 (20060101); H04M 19/02 (20060101); H04L 7/033 (20060101); H04M 001/00 ()

Expiration Date: 12/26/2017