Patent Number: 6,167,364

Title: Methods and apparatus for automatically generating interconnect patterns in programmable logic devices

Abstract: Methods and apparatus are described for generating circuit parameters for a plurality of interconnect line circuit models. The plurality of circuit models represent a plurality of interconnect lines in a programmable logic device (PLD). Design description data corresponding to the PLD are generated at least in part from spreadsheet representations of the plurality of interconnect lines. A device model for the PLD is generated using estimated circuit parameters and a plurality of mathematical equations representing the plurality of interconnect line circuit models. Operation of the PLD is simulated using the device model and the design description data thereby generating modeled delay data corresponding to the estimated circuit parameters. The modeled delay data are compared with measured delay data corresponding to the plurality of interconnect lines. Where all of the modeled delay data are within an error limit of corresponding measured delay data, the estimated circuit parameters are designated as the circuit parameters.

Inventors: Stellenberg; Daniel S. (Santa Clara, CA), Karchmer; David (Sunnyvale, CA)

Assignee: Altera Corporation

International Classification: G06F 17/50 (20060101); G06F 017/50 (); G06G 007/62 ()

Expiration Date: 12/26/2013