Patent Number: 6,167,416

Title: System and method for RAM-partitioning to exploit parallelism of radix-2 elements in FPGAS

Abstract: A system and method are disclosed for providing highly parallel, FFT calculations in a circuit including a plurality of RADIX-2 elements. Partitioned RAM resources allow RADIXes at all stages to have optimal bandwidth memory access. Preferably more memory is made available for early RADIX stages and a "critical" stage. RADIXes within stages beyond the critical stage preferably each need only a single RAM partition, and can therefore simultaneously operate without fighting for memory resources. In a preferred configuration having P RAM partitions and P RADIX stages, the critical stage is stage number log.sub.2 P, and until the critical stage, only P/2 RADIX elements can simultaneously operate within each stage. After the critical stage, all RADIXes within each stage can simultaneously operate.

Inventors: Verma; Hare K. (Campbell, CA), Nag; Sudip K. (San Jose, CA)

Assignee: Xilinx, Inc.

International Classification: G06F 17/14 (20060101); G06F 015/00 ()

Expiration Date: 12/26/2017