Patent Number: 6,167,418

Title: Byte-switching arithmetic unit

Abstract: The present invention provides a byte-switching arithmetic unit comprising at least three stages, each of which has a plurality of two-input selectors operable in a predetermined minimum bit width unit, the byte-switching arithmetic unit having two inputs of a predetermined input bit width, wherein a first stage has a first number of first stage two-input selectors where the first number corresponds to a quotient of a division to the predetermined input bit width by the predetermined minimum bit width unit, wherein a second stage has a second number of second stage two-input selectors where the second number corresponds to a half of the first number so that the second stage two-input selectors receive a half of outputs from the first stage two-input selectors, and wherein a third stage has a third number of third stage two-input selectors where the third number also corresponds to the half of the first number so that the third stage two-input selectors receive both a half of outputs from the second stage two-input selectors and a half of outputs from a remaining half group of the first stage two-input selectors.

Inventors: Suzuki; Kazumasa (Tokyo, JP)

Assignee: NEC Corporation

International Classification: G06F 7/76 (20060101); G06F 007/38 (); G06F 007/52 ()

Expiration Date: 12/26/2017