Patent Number: 6,167,484

Title: Method and apparatus for leveraging history bits to optimize memory refresh performance

Abstract: A method and apparatus that improves either power savings and/or DRAM system access bandwidth in an embedded DRAM device. The apparatus (200, 800, or 900) contains embedded DRAM memory devices (212, 802, or 902) which require refresh operations in order to retain data. As the memory devices (212, 802, or 902) are accessed by read and write system operations and by refresh operations, a set of history bits (204, 808, 904) are continually updated to indicate a level of freshness for the charge stored in various DRAM memory rows. When scheduled refresh opportunities arrive for each memory row in the embedded DRAM devices, the history bits (204, 808, 904) are accessed to determine if the refresh operation of a row of memory should be performed or if the refresh operation should be postponed until a subsequent refresh time period.

Inventors: Boyer; John Mark (Austin, TX), Bruce, Jr.; William Clayton (Austin, TX), Giles; Grady Lawrence (Austin, TX), Johnston; Thomas K. (Austin, TX), Pappert; Bernard J. (Austin, TX), Vaglica; John J. (Austin, TX)

Assignee: Motorola, Inc.

International Classification: G11C 7/00 (20060101); G11C 7/24 (20060101); G11C 11/406 (20060101); G11C 007/00 ()

Expiration Date: 12/26/2017