Patent Number: 6,167,486

Title: Parallel access virtual channel memory system with cacheable channels

Abstract: A memory system having a main memory which is coupled to a plurality of parallel virtual access channels. Each of the virtual access channels provides a set of memory access resources for controlling the main memory. These memory access resources include cache resources (including cache chaining), burst mode operation control and precharge operation control. A plurality of the virtual access channels are cacheable virtual access channels, each of which includes a channel row cache memory for storing one or more cache entries and a channel row address register for storing corresponding cache address entries. One or more non-cacheable virtual access channels are provided by a bus bypass circuit. Each virtual access channel is addressable, such that particular memory masters can be assigned to access particular virtual access channels.

Inventors: Lee; Jeffery H. (Sunnyvale, CA), Ando; Manabu (Los Gatos, CA)

Assignee: NEC Electronics, Inc.

International Classification: G06F 12/08 (20060101); G06F 013/16 ()

Expiration Date: 12/26/2013