Patent Number: 6,167,497

Title: Data processing apparatus and register address translation method thereof

Abstract: A data processing apparatus includes physical registers larger in number than logical registers specified by a register specification field of an instruction executed by the apparatus. The physical registers are classified into a plurality of banks. In response to a particular instruction, an execution control section supplies a register address converter with bank information to select a bank of the physical register. The converter stores the bank information in a bank register. Receiving logical register address information specified by the register specification field of the instruction, the address converter adds the bank information set to the bank register to at least a portion of the logical register address information, thereby producing a physical register address which can specify any one of the physical registers.

Inventors: Nakatsuka; Yasuhiro (Koganei, JP), Katsura; Koyo (Hitachiota, JP)

Assignee: Hitachi, Ltd.

International Classification: G06F 9/318 (20060101); G06F 9/30 (20060101); G06F 012/02 ()

Expiration Date: 12/26/2017