Patent Number: 6,167,498

Title: Circuits systems and methods for managing data requests between memory subsystems operating in response to multiple address formats

Abstract: A process and implementing computer system in which a graphics subsystem 117 having an XY coordinate addressing system interfaces with a host computer system having a linear addressing configuration. The subsystem includes an internal graphics engine 325. The system CPU initiates data fetch and write requests to the host computer system memory 109. A subsystem host-XY circuit processes address requests between the subsystem and the host through the host system bus 105. A host system bus master circuit 315 is included in the subsystem 117 and is responsive to the host-XY circuit to access the host system bus 105 and effect the transfer of requested data through subsystem queuing units 303, 307 to the subsystem host interface bus 301 from which such requested data may be acquired by the graphics engine 325. In an alternate embodiment, the subsystem includes a subsystem master control unit or MCU to enable parallel or simultaneous operation of the Host XY unit and the graphics subsystem MCU.

Inventors: Larson; Michael Kerry (Austin, TX), McDonald; Timothy James (Austin, TX)

Assignee: Cirrus Logic, Inc.

International Classification: G09G 5/39 (20060101); G09G 5/36 (20060101); G06F 012/00 ()

Expiration Date: 12/26/2013